GTLP16612 |
RFQ for GTLP16612 Required Field |
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| Technical/Catalog Information | GTLP16612MEA |
| Vendor | Fairchild Semiconductor |
| Category | Integrated Circuits (ICs) |
| Number of Circuits | 18-Bit |
| Package / Case | 56-SSOP |
| Logic Type | Universal Bus Transceiver |
| Packaging | Tube |
| Mounting Type | Surface Mount |
| Number of Inputs | - |
| Current - Output High, Low | 32mA, 32mA |
| Supply Voltage | 3.15 V ~ 3.45 V |
| Operating Temperature | -40°C ~ 85°C |
| Voltage - Supply | 3.15 V ~ 3.45 V |
| Drawing Number | * |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | GTLP16612MEA GTLP16612MEA |
| Product | Manufacturers | Pack | D/C | |||||
| GTLP16612 | - | TSSOP | 05+ |
The GTLP16612 is an 18-bit universal bus transceiverwhich provides TTL to GTLP signal level translation. Thedevice is designed to provide a high speed interfacebetween cards operating at TTL logic levels and a back-plane operating at GTLP logic levels. High speed back-plane operation is a direct result of GTLP's reduced outputswing (<1V), reduced input threshold levels and outputedge rate control which minimizes signal settling times.GTLP is a Fairchild Semiconductor derivative of the Gun-ning Transceiver Logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-cess, Voltage, and Temperature (PVT) compensated. Itsunction is similar to BTL or GTL but with different driveroutput levels and receiver threshold. GTLP output low volt-age is typically less than 0.5V, the output high is 1.5V andhe receiver threshold is 1.0V.
Features |
| Bidirectional interface between GTLP and TTL logiclevels Designed with Edge Rate Control Circuit to reduceoutput noise VREF pin provides external supply reference voltage forreceiver threshold Submicron Core CMOS technology for low powerdissipation Special PVT Compensation circuitry to provide consis- tent performance over variations of process, supplyvoltage and temperature 5V tolerant inputs and outputs on A-Port Bus-Hold data inputs on A-Port to eliminate the need for external pull-up resistors for unused inputs Power up/down high impedance TTL compatible Driver and Control inputs A-Port outputs source/sink −32 mA/+32 mA Flow-through architecture optimizes PCB layout Open drain on GTLP to support wired-or connection |
